1. Field of the Invention
The present invention relates to interconnects used to attach a microelectronic device to a carrier substrate. In particular, the present invention relates to fabricating a plurality of projections extending from the microelectronic device bond pad to form a compliant interconnect.
2. State of the Art
Various methods are used to make electrical contact between a microelectronic device and a carrier substrate, including but not limited to, TAB bonding, wire bonding, and solder ball interconnects. Solder ball interconnects are particularly useful with microelectronic devices which have a high number of input/output signal connections.
FIG. 5 illustrates an assembly 200 comprising a microelectronic device 202 (illustrated as a flip chip) physically and electrically attached by an active surface 204 thereof to a connection surface 206 of a carrier substrate 208 by a plurality of interconnects 212, such as solder balls, extending between bond pads 214 on the microelectronic device active surface 204 and land pads 216 on the carrier substrate connection surface 206. An underfill material 218 may be disposed between the microelectronic device active surface 204 and the carrier substrate connection surface 206 to prevent contamination and to increase mechanical reliability.
FIG. 6 illustrates a view of a single interconnect comprising a metal column 222, such as a copper column, formed on the microelectronic device bond pad 214. The metal column 222 is used for achieving a sufficient current flow through each interconnect 212 and to prevent electromigration, as will be understood to those skilled in the art. The metal column 222 is attached to the carrier substrate land pad 216 with a layer of conductive adhesive 224, such as a solder material. A resist material 226 may be patterned to contain the conductive adhesive 224, as known in the art, prior to the attachment of the metal column 222.
The metal column 222 is usually has an aspect ratio (height to width) of between about 1 and 2. The metal column 222 is also usually made of a highly conductive material, such as copper, gold, tin, and the like. However, such highly conductive materials generally have a high elastic modulus. The high elastic modulus of the metal column 222 coupled with a large coefficient of thermal expansion (“CTE”) mismatch between the microelectronic device 202, and the carrier substrate 208 can generate significant stresses, which is transferred to thin films which make up at least a portion of the integrated circuitry (not shown) on the microelectronic device active surface 204. These stresses can result in cracking and/or delamination of these thin films. The potential for cracking and delamination is a particular concern in the use of low K dielectric materials, such as CDO, SiLK, fluorocarbons, and the like, used in the fabrication of the build-up layers. Of course, such cracking and/or delamination can result in the failure of the microelectronic device 202.
Therefore, it would be advantageous to develop an interconnect that reduces or substantially eliminates the possibility of cracking and/or delamination, and processes for forming the interconnect.